1. Field of the Invention
This invention relates to improvements in vertical PNP transistors and methods for making same in digital BiCMOS processes, and more particularly to improvements in methods for building high F.sub.t, isolated, vertical PNP transistors in standard non-oxide-isolated digital BiCMOS twin well DUF (buried layer) processes.
2. Relevant Background
An accelerating trend in the integrated circuit industry is the merging of analog and digital functions onto the same semiconductor substrate on which an integrated circuit is constructed. Factors such as overall system speed, reliability, and board space are all involved in forcing this trend. In these so-called "mixed-signal" designs, the digital content is usually much higher than the analog content. Consequently, the choice of integrated circuit process technology usually involves adding the necessary analog components onto an existing digital manufacturing process.
Digital BiCMOS processes are usually the starting process of choice, since they combine the CMOS components for digital applications together with high-speed (F.sub.t .gtoreq.10 GHz) NPN devices needed for the analog functions. However, most digital BiCMOS processes emphasize bipolar NPN devices, without providing a suitable isolated PNP device. If any such PNP device is available, it is typically a lateral PNP device, which is very slow, with F.sub.t values in the range of about 10 MHz. Therefore, such PNP devices are generally not suitable for use in the signal path, hampering the ability to design cost-effective high-speed analog functions.
The concept of integrating isolated vertical PNP transistors into an existing junction-isolated BiCMOS process is addressed in U.S. Pat. No. 4,855,244 by Hutter and Trogolo, which describes a LinBiCMOS process. While this patent discusses the use of an N- buried layer region for vertically isolating a P-type DUF region from a P-type substrate, the description is in the context of a standard N+ buried layer process, rather than a twin well DUF process.
What is needed, therefore, for mixed-signal process technologies is a low cost method for building high F.sub.t, isolated, vertical PNP transistors in a standard non-oxide-isolated digital BiCMOS twin well DUF process.